VLIW是什么意思 VLIW在线翻译 VLIW什么意思 VLIW的意思 VLIW的翻译 VLIW的解释 VLIW的发音 VLIW的同义词 VLIW的反义词 VLIW的例句 VLIW的相关词组

超长指令字；

1. VLIW

1. Use the TSMC 0.13um process to do synthesis analysis. Under same performance, the register file area of composite FU is 10% more than RISC and 50% less than VLIW.
    使用台积电0.13um制程作合成分析，在同样的运算效能下，复杂运算单元较简化指令集合的面积约多10%，但较超长指令减少约50%。

2. VLIW的翻译

2. Recently, we have seen that VLIW has been regaining popularity as means to improve performance.
    最近，我们看到了VLIW已重新流行的手段来提高业绩。

3. VLIW

3. This paper presents the design of a highly re-configurable 64-bit adder, which is well suitable for VLIW digital signal processor.
    描述了一款适用于超长指令字数字信号处理器的64位加法器的设计。

4. Decreasing code size to fit into cost- or space-constrained memory systems is important business these days.
    VLIW 松散的程式结构对记忆体的使用而言是不好的。

5. VLIW什么意思

5. The debate between the merits of superscalar and VLIW is not only restricted to the GPP universe.
    之间的辩论的优点超标和VLIW指令不仅限于优良药房工作规范宇宙。

6. LIW isn`t a magic bullet, but it`s the new wave in microprocessor design. Within a few years, it`s certain that at least some of your software will be running on VLIW chips.
    ILW不是一颗魔法子弹，但它是微处理器设计的新的高潮，在几年以内，至少你的一部分软件将会在VILW集成块上运行。

7. We know that a key difference between superscalar and VLIW lies in the hardware and software complexity respectively.
    我们知道，一个关键区别在于超标量和超长指令字中的硬件和软件的复杂性分别。

8. Finally, a VLIW machine model is designed, on which the improved DESP algorithm is simulated and shown to be correct.
    最后，将改进的DESP算法在 VLIW机器模型上进行了模拟，说明了算法的正确性。

9. VLIW是什么意思

9. It is found that loop-carried flow dependencies form a set of disjoint linear ordered sets, and that there is one and only one basis that is independent and inclusive, making unnecessary all the other dependencies.
    利用这一性质，围绕着包含这一概念，该文为VLIW结构上的流相关分析提出了一个完整的娄学模型，发现体间流相关集合可划分为若干不相交的线序集合，存在且仅存在一个独立的、全包含的流相关集合，使其他所有流相关都不必要。

10. VLIW

10. An architecture and design of hardware loop buffer for a VLIW DSP is provided.
    提出了用于VLI WDSP处理器的硬件循环缓冲器的设计。

11. This paper surveys the current state and prospect of it, and deeply analysis several possible architectures (VLIW. one - chip multiprocessors. multithreading, etc.)following the superscalar.
      本文先对微处理器的现状作一介绍，展望它的未来发展，深入分析微处理器体系结构继超标量技术后可能的几个主要发展方向（VLIW、单芯片多处理器、多线程等）的优劣。

12. Quantitatively analyzing the factors which influence global software pipelining and presenting a new global software pipelining algorithm which is better than the existing global software pipelining algorithms.
      研究并参与设计基于URPR算法的新型VLIW信号处理机体系结构URPR-1，该体系结构中的流水寄存器堆为优化编译器提供了有效的硬件支持，从而使编译器生成更优的目标代码。

13. In order to reduce the conflict of L1P in CMT, we propose the policy of logic partition L1P Cache by n power of 2 and the competing loop lock. Now the fairness researchs always need single thread sample phase, we propose a novel fairness policy:FROCM, it doesn't need single thread sample phase. We propose ring cooperant L1 data Cache, which can reduce both the complexity of the design and the load of L2 Cache. We also propose a method to exchange threads dynamicly based on fast-shared data pool, it can detect the data consanguinity of two threads in real time and exchange them into one core rapidly. At last, we design and implement a dual-core and dual-thread VLIW prototype YHFT DSP/DS based on the above studies. In order to enhance the bandwidth of data path and reduce the delay of critical path delay of CMT processor, we design a 10R/6W register file full customly.
      为了减小多线程运行时指令Cache的冲突，本文提出了二幂等分指令Cache策略和循环锁竞争机制；现有对CMT处理器公平性的研究常常需要中断其它线程进行单线程采样，针对这个问题本文提出了多线程公平性策略FROCM；本文提出了环形协同数据Cache结构，以解决CMT处理器中共享存储体负载重，冲突大的问题；本文还提出了基于快速共享数据缓冲池的线程动态交换技术；最后本文实现了一个双核同时多线程芯片原型YHFT DSP/DS。

14. In a VLIW processor implementation, decoding of one token is pipelined with the inverse scan and inverse quantisation step of the preceding token.
      在VLIW处理器实现中，一个标记的解码与前一标记的反向扫描和反量化步骤被流水线处理。

15. Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism (ILP) by VLIW.
      新一代面向密集计算的高性能处理器普遍采用分布式寄存器文件来支撑ALU阵列，并通过VLIW开发指令级并行。

16. VLIW在线翻译

16. The design of shared data register file is the hardest for implementation of VLIW (Very Long Instruction Word) DSP (Digital Signal Processing) Processors.
      共享数据寄存器堆设计是超长指令字DSP处理器实现的难点。

17. VLIW

17. Design and Implementation of VLIW Processor System Level Verification Platform
      VLIW处理器系统级验证平台的设计与实现

18. Modern digit signal processor (DSP) achieve instruction level parallelism with superscalar or very long instruction word (VLIW).
      现代数字信号处理器（DSP）一般采取超长指令字或是超标量来实现指令级并行。

19. Very long instruction word digit signal processor will assign recognition and scheduling of parallel task to compiler, so we need a very ambitious complier to use VLIW DSP well.
      超长指令字（VLIW）数字信号处理器将并行任务的识别和调度交给了编译器，因此在利用VLIWDSP的时候需要有一个功能更为强大的编译器。

20. VLIW

20. A general purpose programming language, like C, and its compiler can not automatically generate codes for a VLIW processor's special purpose function units.
      通用的高级程序设计语言的编译器，比如C的编译器，不会为VLIW处理器的特殊功能部件自动生成代码。